Description
Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT https://WebToolTip.com Published 3/2025
Created by Aleksei Rostov
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Beginner | Genre: eLearning | Language: English | Duration: 10 Lectures ( 2h 17m ) | Size: 1.91 GB
Practical FPGA DSP with Xilinx IP cores (FIR, CIC, DDS, FFT): from simulation to real-time deployment on Zynq 7000
What you'll learn
How to Simulate Xilinx DSP IP cores (FIR, CIC, DDS compiler and FFT) in Vivado with Verilog testbenches & Python analysis
How to Integrate IP cores into FPGA designs on development board
How to Develop standalone embedded C application to interface with DSP IP cores
How to Automate Vivado & Vitis workflow with TCL and Python scripts
Requirements
Vivado 2024.2
Vitis 2024.2
Python >= 3.0
Powershell
Any development board with Zynq 7000 SoC (Arty z7-20 as example)