Udemy - Simple Axi Bus Design Using Verilog Hdl

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Category:
 Other
Date:
01/11/24 at 5:54pm GMT+1
Submitter:
Unknown
Seeders:
2
Leechers:
0
File size:
595 MB in 26 files

Torrent Status:
  This torrent has been verified.

Infohash:
47a78a95dfa3a4b293ce07513d9acde273ff6439


File list

  • Udemy - Simple Axi Bus Design Using Verilog Hdl
  • icon ~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4 22.5 MB
    icon ~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4 6.3 MB
    icon ~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4 12.9 MB
    icon ~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4 15.1 MB
    icon ~Get Your Files Here !/2 - AXI bus/11 - Dependencies between channel handshake signals.mp4 10.9 MB
    icon ~Get Your Files Here !/2 - AXI bus/4 - Introduction to AXI.mp4 6.1 MB
    icon ~Get Your Files Here !/2 - AXI bus/5 - AXI channel Architecture of Readwrites.mp4 17.6 MB
    icon ~Get Your Files Here !/2 - AXI bus/6 - AXI signals.mp4 12 MB
    icon ~Get Your Files Here !/2 - AXI bus/7 - Handshaking signals.mp4 12 MB
    icon ~Get Your Files Here !/2 - AXI bus/8 - Signal Diagram.mp4 20 MB
    icon ~Get Your Files Here !/2 - AXI bus/9 - Write process Timing diagram.mp4 12.1 MB
    icon ~Get Your Files Here !/3 - Implementation of Simple AXI bus/12 - AXI state machine for write read.mp4 2.4 MB
    icon ~Get Your Files Here !/3 - Implementation of Simple AXI bus/13 - AXI MasterSlave Block diagram and Writeread process.mp4 11.1 MB
    icon ~Get Your Files Here !/4 - Source code/14 - axi-master-write.v 3.1 KB
    icon ~Get Your Files Here !/4 - Source code/14 - axi-slave-write.v 2.7 KB
    icon ~Get Your Files Here !/4 - Source code/14 - Design of AXI bus using verilog HDL write process.mp4 279.4 MB
    icon ~Get Your Files Here !/4 - Source code/15 - axi-master-read.v 2.5 KB
    icon ~Get Your Files Here !/4 - Source code/15 - axi-slave-read.v 2.2 KB
    icon ~Get Your Files Here !/4 - Source code/15 - Design of AXI bus using verilog HDL Read process.mp4 123.3 MB
    icon ~Get Your Files Here !/4 - Source code/16 - AXI master slave.mp4 12.8 MB
    icon ~Get Your Files Here !/4 - Source code/16 - axi-master.v 1.6 KB
    icon ~Get Your Files Here !/4 - Source code/16 - axi-slave.v 1.5 KB
    icon ~Get Your Files Here !/4 - Source code/17 - design.sv 188 B
    icon ~Get Your Files Here !/4 - Source code/17 - Test bench simulation.mp4 19 MB
    icon ~Get Your Files Here !/4 - Source code/17 - testbench.sv 2.3 KB
    icon ~Get Your Files Here !/Bonus Resources.txt 386 B

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